In data processing systems having virtual memory capabilities, a memory management unit (MMU) is provided to translate each "logical" address in virtual memory as it is output by the data processor to a respective "physical" address in real memory. In general, upon initiation of system operation, the MMU is in a non-translation mode so that each logical address is provided as the respective physical address without translation. After the operating system has initialized all appropriate logical-to-physical address translation information in the MMU or in memory, as the case may be, the MMU can be put into the normal translation mode. Thereafter, the MMU will translate all logical addresses output by the processor to the respective physical addresses according to the translation information established by the operating system.
In some systems, the MMU can be selectively enabled and disabled by means of a control bit in a register within the MMU, which can be set or reset by the processor. For example, in at least one prior art system, the MC68851 Paged Memory Management Unit (PMMU), commercially available from Motorola, Inc., the state of an Enable bit in a Translation Control register, directly writable (and readable) by the associated processor, controls the translation mechanism. When "set", translation is enabled; when "clear", translation is disabled.
In systems used for emulation or software/hardware development, the operation of the data processing system may be monitored by an independent controller to verify proper system operation. In such systems, it is often difficult to observe certain system events, such as cache activities. Accordingly, in some systems, the cache can be dynamically disabled by the monitoring controller as required. An example of such a dynamic cache disabling mechanism is described in U.S. Pat. No. 4,740,889 issued to David S. Mothersole et al. on Apr. 26, 1988, and assigned to Motorola, Inc.
During emulation, the monitoring activities of the emulation software executing within the processor may affect the state of the MMU such that the performance of the software under test is not as it would have been absent those effects. For example, execution of the emulation software will modify the state of the "use" information used to select translation descriptors for replacement, so that when execution of the test software is resumed, the replacement algorithm will not perform the same as when only the test software has been executing. Even if the MMU is capable of being selectively disabled from the processor, sufficient translation activities still occur while the disabling code is being executed. What is needed is a mechanism for dynamically disabling the MMU independent of the processor.